In prior processor-cache configurations, the cache memory receives the same clock signal as the processor. Timings between the processor and cache were standard synchronous relationships. The timing relationships are described by the following equations.
Maximum delay time must be considered when determining the clock period for a circuit. The clock period is given by the following equation: EQU t.sub.p.gtoreq.t.sub.cd(max) +t.sub.ft(max) +t.sub.su +t.sub.cksk
where t.sub.p represents the clock period, t.sub.cd(max) represents the maximum clock to signal delay time, t.sub.ft(max) represents the maximum flight time for a given signal, t.sub.su represents the required signal set up time, and t.sub.cksk represents clock skew.
Hold time is determined using the following equation: EQU t.sub.cd(min) +t.sub.ft(min).gtoreq.t.sub.h +t.sub.cksk
where t.sub.cd(min) represents the minimum clock to signal delay time, t.sub.ft(min) represents minimum flight time, t.sub.h represents the required hold time and t.sub.cksk represents clock skew.
Above a certain frequency, it is impossible to satisfy both equations because of the delay introduced by skew and the relationship between t.sub.cd(min) /t.sub.cd(max) and t.sub.su /t.sub.h.
It is possible to extend the frequency of operation beyond the limit of these equations by using source synchronous signaling. In source-synchronous signaling, timing information is passed with signals to compensate for t.sub.cd and t.sub.ft terms. Maximum frequency of operation is limited by the t.sub.su /t.sub.h window, the ability to control signal skews, and the ability to manage signal integrity.
In the prior art, source-synchronous signaling has been used in asynchronous system interfaces and with a lower frequency common clock. The present invention discloses another method to use source-synchronous signaling for a high speed memory interface. It is based on the assumption that memory is always a slave device accessed by a master device (i.e., the controller). By allowing the time base to track system delays, it is possible to maximize the signaling rate with minimal latency impact. For purposes of description, the controller is assumed to be in a CPU controlling a cache memory; however, it may also be used in any other master/slave interface. Because the delay accumulates around the loop from CPU to cache and back to CPU, the CPU must wait for maximum loop delay time (rounded to the next clock) and a deskew latch must hold data to account for the minimum loop delay time.